The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor includes a gate electrode as a control electrode overlying a semiconductor substrate and spaced-apart source and drain regions in the substrate between which a current can flow. A gate insulator is disposed between the gate electrode and the semiconductor substrate to electrically isolate the gate electrode from the substrate. A control voltage applied to the gate electrode controls the flow of current through a channel in the substrate underlying the gate electrode between the source and drain regions. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
A Fin field-effect transistor (FinFET) is a type of transistor that lends itself to the dual goals of reducing transistor size while maintaining transistor performance. The FinFET is a three dimensional transistor formed in a thin fin that extends upwardly from a semiconductor substrate with a gate electrode structure disposed over and around the fin. Transistor performance, often measured by its transconductance, is proportional to the width of the transistor channel. In a FinFET the transistor channel is formed along the vertical sidewalls of the fin or on both vertical sidewalls and the top horizontal plane of the fin, so a wide channel, and hence high performance, can be achieved without substantially increasing the area of the substrate surface required by the transistor.
Transistor performance is also impacted by surface topography of the gate electrode structure. During formation of the gate electrode structure, a gate dielectric layer and a gate electrode layer are formed over the fins and over the semiconductor substrate outside of the fins to form a gate electrode structure, resulting in a stepped configuration with raised portions of the gate electrode structure over the fins and sunken portions over the semiconductor substrate outside of the fins. Planarity between the raised portions and the sunken portions is generally desired for optimal transistor performance, with various techniques such as chemical-mechanical planarization (CMP) or partial CMP and reactive ion etching (RIE) employed to planarize the raised portions. However, existing techniques are ineffective to planarize the raised portions without introducing variations in surface planarity because the techniques rely upon removing a fixed amount of material, and different pattern densities result in different heights of raised portions in areas of different pattern densities after planarizing. Variations in surface planarity also generally increase as more material is removed due to the differences in pattern density. As a result, it is difficult to reduce variation in surface topography below 500 Å.
Accordingly, it is desirable to provide methods of forming integrated circuits with a planarized layer, methods of forming devices such as FinFETs that include the planarized layer, and devices that include a planarized layer with minimized variations in surface planarity. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.